An integrated circuit (“IC”) is a device (e.g., a semiconductor device) that includes many electronic components, such as transistors, resistors, diodes, etc. These components are often interconnected to form multiple circuit components, such as gates, cells, memory units, arithmetic units, controllers, decoders, etc. An IC includes multiple layers of wiring that interconnect its electronic and circuit components. Traditionally, IC's use preferred direction (“PD”) wiring models, which specify a preferred wiring direction for each of their wiring layers. In preferred direction wiring models, the preferred direction typically alternates between successive wiring layers.
One example of a PD wiring model is the PD Manhattan wiring model, which specifies alternating layers of preferred-direction horizontal and vertical wiring. Another example of a PD wiring model is the PD diagonal wiring model, which specifies alternating layers of preferred-direction diagonal wiring. The PD diagonal wiring model can allow for shorter wiring distances than the PD Manhattan wiring model and can decrease the total wirelength needed to interconnect the electronic and circuit components of an IC.
Design engineers design IC's by transforming logical or circuit descriptions of the IC's into geometric descriptions, called layouts. To create layouts, design engineers typically use electronic design automation (“EDA”) applications. These applications provide sets of computer-based tools for creating, editing, and analyzing IC design layouts. IC layouts include geometric representations of IC elements that are to be fabricated on a wafer, such as IC components, interconnect lines, via pads, etc. As such, IC layouts typically include several geometries such as (1) circuit modules (i.e., geometric representations of electronic or circuit IC components) with pins, (2) interconnect lines (i.e., geometric representations of wiring) that connect the pins of the circuit modules on a same layer, and (3) vias (i.e., geometric representations of non-planar wiring) that connect the pins of the circuit modules across different layers.
To fabricate an IC after designing of the IC layout is completed, a lithographic plate (photomask) is created based on the IC layout so that the photomask contains the various geometries of the IC layout. The various geometries contained on the photomask represent the IC elements (such as IC components, interconnect lines, via pads, etc.) to be created on a wafer in a particular circuit pattern, the wafer forming the base of the integrated circuit. The wafer will typically have a protective insulation layer and a light-sensitive photoresist layer placed on top. A light source and lens are used to focus light through the photomask onto the photoresist layer of the wafer so that selected areas of the photoresist layer are modified (typically weakened or strengthened). In doing so, the circuit pattern represented on the photomask is “imprinted” on the photoresist layer of the wafer. The modified areas of the photoresist layer (as well as the insulation layer beneath) is then etched away to produce the IC elements of the desired circuit pattern. Through multiple stages of designing, photomasking (lighting), and etching, multiple layers of the IC are created.
Typically, however, there is substantial disparity in the geometries as originally designed in the IC layout (and replicated on the photomask) and the resulting fabricated geometries actually produced on a wafer through the photomasking and etching processes. The disparity between the geometries designed in a layout and the resulting fabricated geometries is largely due to the fact that, in recent years, geometry dimensions have become smaller than the wavelength of light used in the photomasking process, thus making accurate reproduction of geometry dimensions problematic. In response, various optical methods, such as Resolution Enhancement Techniques (RET), have been developed to allow more accurate reproduction of geometry dimensions at sizes smaller than the wavelength of light used in the photomasking process. Use of Resolution Enhancement Techniques in IC fabrication, however, do not guarantee that geometries actually fabricated on a wafer will resemble (within a predetermined toleration threshold) the geometries originally designed in an IC layout.
Disparity between a geometry designed in a layout and the resulting fabricated geometry is also caused by diffracted light that strikes the geometry from surrounding geometries, the light being diffracted off the surrounding geometries during the photomask processing of the surrounding geometries. This diffracted light can cause distortions or inaccuracies in the appearance of a geometry with which it makes contact. As such, with or without the use of RET, there is a degree of unpredictability in the fabrication of geometries on a wafer.
FIG. 1 shows an example of the variation that may result between an original geometry 105 as designed in an IC layout (and replicated on a photomask) and a fabricated geometry 120 actually produced on a wafer. In the example of FIG. 1, the original geometry 105 has five features of interest that are indicated by dots: four corner features 110 and one line-point feature 112. As shown in FIG. 1, the fabricated geometry 120 has four rounded corners 125 and a curved line segment 127. Typically in IC fabrication, the corners 125 of a geometry 120 produced on a wafer will have substantial error (i.e., will differ substantially from the corners 110 of the original geometry 105). Also, line segments of a fabricated geometry 120 can also have substantial error and be curved instead of straight, as shown in the example of FIG. 1.
Conventionally, modifications are made to geometries in the IC layout (and replicated on a photomask) to adjust for the errors in the resulting geometries fabricated on the wafer. FIG. 2 shows an example of modifications (correcting shapes) 230 placed on the original geometry 105 and a fabricated geometry 235 actually produced on the wafer. As shown in FIG. 2, the modifications 230 are placed at the corner features 110 of the original geometry 105 which produces less rounded corners 240 in the fabricated geometry 235. A modification 230 is also placed at the line-point feature 112 of the original geometry 105 which produces a less curved line segment 242 in the fabricated geometry 235. Note that although the fabricated geometry 235 produced through use of the modifications 230 is closer in appearance to the original geometry 105, there is still some disparity between the fabricated geometry 235 and the original geometry 105. Typically, modifications are made to original geometries to produce only satisfactory resulting geometries that are within an allowable threshold of variance from the original geometries.
Presently, there are two methods for creating modifications to original geometries in layouts. The first is a simulation-based approach where initial modifications are made to an original geometry in a layout and a computed simulation is performed on the original geometry to produce a simulated geometry. The simulated geometry is used to judge whether the modifications to the original geometry are satisfactory or not. If the modification to the original geometry has not produced a satisfactory simulated geometry, the modification is adjusted (e.g., made larger or smaller) and another simulated geometry is produced. This process is iterated until a satisfactory simulated geometry is produced. The simulation-based approach, however, requires that every geometry in a layout be iteratively simulated until a satisfactory geometry is produced. Considering that there may be billions of such geometries on a single layout, this approach can be very time intensive.
The second approach is a rule-based approach where modification rules are typically developed by an IC designer by hand. Such rules define what modifications are to be made to geometries in different situations. Although the rule-based approach is not as time-intensive as the simulation-based approach, a large number of rules must be developed to cover the various situations that may arise in an IC layout. Also, each modification rule may be complex and cumbersome to develop and apply.
As such, there is a need for a simple and efficient method for determining a modification to a geometry in layout that is calculated to produce a satisfactory geometry when fabricated on a wafer.